STA Engineer

KEY RESPONSIBILITIES: Responsible for Multi Voltage domain STA setting setup, execution and timing closure of GPU Drive the pre-route timing checks and Qo R clean up to eliminate SDC issues and ensure a quality handoff for STA checks Ensuring timing correlation between Pn R STA and timely feedbacks to PD team Generating block level HS session and using Top context from So C for Block-So C Interface timing closure. Generating timing ECO using Tweaker/Prime Closure.

PREFERRED EXPERIENCE: 3+ GHz range) Analyzing the timing reports and identifying both design and constraints related issues. Worked on blocks with multiple power and voltage domains Preferred EDA tool experience: Primetime, Tweaker/Prime Closure, Innovus Robust Understanding of DFT modes requirements for timing signoff Good understanding of physical design flow and ECO implementation Strong understanding of SDC constraints, OCV, AOCV, POCV analysis Robust TCL/scripting knowledge is mandatory.

ACADEMIC CREDENTIALS: Bachelors or Masters degree in Electrical Engineering

📌 Sta Engineer Bengaluru (India)
🏢 MediaTek
📍 India