? Job Title: DFT Engineer (Senior / Manager)

?Experience Required: 3 to 15 Years ?Annual CTC Budget: Best in Industry / Standard Market Competitive LPA ?Location: Bangalore, India

⚠️MANDATORY CRITICAL MATCH CRITERIA (READ FIRST):

✅Experience: 3 to 15 years of dedicated experience in DFT (Design for Testability). Min 2 years stability per org. ✅Education: B.E. / B.Tech / M.E. / M.Tech in Electronics, VLSI, or related fields. ✅Core Skills: Hands-on execution of BSCAN, MBIST, SCAN, ATPG pattern generation, and coverage improvement. ✅Software/Tools: Proficiency in standard toolsets from Cadence, Siemens Tessent, or Synopsys, alongside simulators like VCS, NCSim, or Xcelium. ✅Communication: Exceptional English skills for cross-functional collaboration, customer alignment, and team mentoring. ✅Logistics: Hybrid / Office-based model located in Bangalore, India.

➡️Position Overview

Drive SoC-level DFT architecture and implementation across complex silicon projects from concept to silicon bring-up. The role focuses on executing scan, MBIST, ATPG, and timing simulations while providing critical test-mode constraints to STA/PD teams.

? Core Responsibilities

✔️Design & Integration:



Execute BSCAN, MBIST, Scan insertion, and OCC/OPCG / EDT compression logic at the SoC level. ✔️Pattern Generation & Debug: Generate TDF, stuck-at, and IDDQ patterns; perform gate-level zero-delay and SDF timing simulations. ✔️Timing & Constraints: Formulate and deliver robust test-mode timing constraints for STA and Physical Design teams. ✔️Post-Silicon Support: Participate in silicon bring-up and ATE debug using shmoo plots and graphs to drive yield optimization. ✔️Team Leadership: Lead technical reviews, mentor junior DFT engineers, and coordinate effectively across cross-functional teams.

How to Apply ? If you meet the requirements outlined in the and are interested in this prospect, please email your resume to [email protected] , mentioning your current CTC, expected CTC, and Notice Period. Alternatively, click the "Apply" button directly on this platform. Applications failing to meet baseline metrics will be automatically filtered.

#DFTEngineer #Tessent #Synopsys #ATPG #MBIST #VLSI #Semiconductor #BangaloreJobs

📌 DFT Engineer (Senior/Manager) (Bengaluru)
🏢 Amrapali Solutions
📍 Bengaluru