Job Title: DFT ATPG Engineer

Location: Bangalore

Experience: 5–8 Years

Role Overview

We are seeking a skilled DFT ATPG Engineer with strong fundamentals and hands‑on experience in test methodologies, debug, and coverage analysis. The ideal candidate will be a collaborative team player who contributes effectively to both technical execution and team growth.

Key Responsibilities

Execute and support Design‑for‑Test (DFT) activities including scan insertion, ATPG, and OCC integration

Perform DRC debug, test coverage analysis, and simulation debug (timing and non‑timing)

Analyze and resolve issues related to testability, fault coverage, and pattern generation

Work with advanced DFT methodologies including SSN, IJTAG (IEEE 1687), ICL, and PDL handling





Collaborate with cross‑functional teams to ensure smooth DFT integration and issue resolution

Contribute to continuous improvement of DFT flows, methodologies, and debug efficiency

Required Skills

IJTAG (IEEE 1687) with ICL & PDL updates

Scan insertion: EDT, OCC / Scan Clocking understanding

Memory BIST (SMS/SMSG)

ATPG concepts (SAF, TDF), coverage improvements, and sims

SSN concepts

Proficiency in AI tools and scripting

Behavioral Competencies

Solid team player with a collaborative mindset

Proactive in learning and sharing knowledge

Effective communication and coordination skills

Ownership‑driven with focus on quality and timely delivery

📌 DFT ATPG Engineer (Bengaluru)
🏢 QTIMINDS
📍 Bengaluru