At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
BTech/ MTech in Engineering
12+ years of VLSI industry experience in Verification.
SOC level verification experience preferred
IP or Subsystem or SOC level verification experience
Should be able to develop test plans, tests
Solid knowledge of SV, UVM. Should be able to create verification environment using UVM methodology
Should be able to develop bus functional models, monitors, checkers and scoreboards.
Should have experience in coverage driven verification closure.
Strong individual contributor with valuable debug, problem solving skills
Working knowledge of verification cycle for any complex IP/SOC for atleast one/more projects.
Lead verification strategy and high quality execution part of SOCs/Chiplet based SOCs.
Mentor and guide verification engineers, fostering technical excellence
Solid experience on complete SOC level Verification Cycle
Ability to collaborate and work seamlessly with design, architecture, and cross‑functional teams

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📌 Sr Principal Design Engineer Hyderabad (India)
🏢 Cadence Design Systems
📍 India