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Experience: 4+ yrs

Location: Hyderabad

Job Type: Full time

We are looking for an experienced Senior SoC / Full-Chip Design Verification Engineer with strong expertise in Gate-Level Simulation (GLS), SystemVerilog, and UVM . The role will focus on pre-silicon verification of complex SoC and full-chip designs, ensuring functional correctness, design robustness, and readiness for silicon.

The ideal candidate will have hands-on experience in GLS, verification environments, regression, debugging, and digital design concepts, with the ability to work on complex verification challenges across the chip development lifecycle.

Requirements

Key Responsibilities

- Perform Gate-Level Simulation (GLS)for SoC and full-chip designs.
- Develop and maintain verification environments using SystemVerilog and UVM .
- Execute pre-silicon verification for complex digital designs and SoC architectures.
- Develop, enhance, and maintain testbenches, test scenarios, and verification components.
- Analyze simulation results and debug functional, timing, and design-related issues.
- Run and maintain regression suites to identify failures and verification gaps.
- Collaborate with RTL designers, architects, and verification teams to resolve design issues.
- Verify complex digital circuits and ensure design functionality against specifications.
- Develop verification plans, test strategies, and coverage-driven verification methodologies.
- Analyze simulation logs, waveforms, and failure patterns to identify root causes.
- Contribute to verification automation and improve regression efficiency.




- Support verification sign-off activities and ensure adequate functional and code coverage.
- Apply assertions/SVA and other verification techniques where applicable.
- Support verification of memory controllers, DRAM interfaces, or other complex subsystems when required.
- Contribute to low-power verification and other advanced verification methodologies as applicable.
- Work with industry-standard simulation, debugging, and verification tools.

What Makes You a Great Fit

- 4+ years of experience in ASIC, SoC, or semiconductor design verification.
- Hands-on Gate-Level Simulation (GLS) experience is mandatory and a deal-breaker.
- Strong proficiency in SystemVerilog (SV), UVM, and Verilog .
- Proven experience in SoC / full-chip pre-silicon verification .
- Strong understanding of digital circuits and RTL-based design concepts.
- Experience developing and maintaining verification environments and testbenches.
- Strong debugging skills across simulation failures, waveforms, logs, and regressions.
- Experience with regression management and verification coverage analysis.
- Good understanding of verification methodologies and pre-silicon validation processes.
- Experience with Assertions / SVA is an advantage.
- Knowledge of DRAM or memory controller verification is a plus.
- Understanding of CMOS concepts and digital/analog circuits is desirable.
- Exposure to low-power verification methodologies is an advantage.
- Scripting and automation skills using languages such as Python, Perl, or Tcl are a plus.
- Experience working with industry-standard simulation and verification tools.
- Strong analytical, problem-solving, and cross-functional collaboration skills.

📌 Design Verification Engineer - GLS (Hyderabad)
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📍 Hyderabad