to drive DFT architecture, methodology, and implementation for
next-generation high-performance SoCs and IPs .
Key ResponsibilitiesDefine end-to-end
DFT architecture and test strategy
for complex SoCsLead
Scan/ATPG, MBIST, LBIST, JTAG, IJTAG and IEEE 1500
implementationsDrive hierarchical DFT integration, test-mode clocking and power-aware test methodologiesOptimize
test time, test data volume and manufacturing costCollaborate with RTL, Architecture, Physical Design and Product/Test Engineering teamsLead DFT verification, post-silicon bring-up,
ATE validation and failure analysisEvaluate and establish DFT flows using leading
EDA tools
Must-Have Skills10–15+ years of hands-on
DFT design, architecture and verificationStrong expertise in
ATPG and advanced fault modelsExperience with
MBIST/BISR and LBISTExpertise in hierarchical DFT and core-wrapper methodologiesProficiency with
Synopsys TestMax/TetraMAX, Siemens Tessent or Cadence ModusStrong understanding of
STA and DFT timing closureStrong scripting skills in
Tcl / Perl / Python / Shell
📌 DFT Engineer (Mumbai)
🏢 Wenger and Watson
📍 Mumbai
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