At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

- BE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer.

- 7+ years of Design Verification experience with SV/UVM

- Strong background on functional verification fundamentals, setting planning, test plan generation, environment development is a must.

- Design Verification experience verifying complex designs and leading projects from concept to verification closure.

- Strong hands-on UVM and System Verilog coding experience and functional verification environment development is required.

Prior experience in IP verification of memory IP (DDR/HBM/GDDR) would be an added advantage.

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📌 Principal Design Engineer (Pune)
🏢 Cadence
📍 Pune