- For Vivado implementation flow testing and QOR analysis
- Looking for engineers with FPGA Vivado tool flow expertise
The
- To validate, test Vivado Implementation flow stages like placer, Static Timing Analysis.
- Person expected to have prior Vivado tool knowledge and FPGA flow awareness.
- Any EDA company experience is nice to have
- Digital design, Logic Design, STA, Design Constraints, Debug skills are basic requirements
Qualifications Experiences
- Bachelors or Masters in ECE, EE, EI, VLSI
- Min 2yrs, Max 4yrs
- Experience in Xilinx Vivado flow, specifically Implementation tool flow
- Experience in FPGA design flow, STA, Logic and System design
- Positive to have automation skills and AI usage knowledge
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