- Candidates with academic/project exposure to PTPX, PrimePower, power analysis or VLSI
- Basic understanding of VLSI Physical Design flow.
- Knowledge of CMOS power concepts – leakage, energetic and switching power.
- Basic hands-on exposure to PTPX / PrimePower is preferred.
- Understanding of STA, timing constraints and SDC.
- Basic knowledge of TCL scripting; Python/Perl is an added advantage.