Title: SoC Verification Engineer for clock tree verification
Role and Responsibilities: Responsible for developing test cases for SoC level clock component level verification scenarios.
Execute Gate level simulations.
Skill Requirements: Hands on experience in SV/UVM based testbench development, assertions coding, Basic knowledge in Bus protocols-APB,AHB,AXI Experience in debugging gate level simulations, low power simulations
Positive to have: Scripting knowledge in Python/Perl