Job Summary

We are seeking an experienced engineer to own Analog/Mixed-Signal IP methodology, packaging, automation, release quality, and reusable design infrastructure. The role focuses on scalable IP delivery flows and consistency of all views required for SoC integration. Hands-on analog circuit design experience is not mandatory.

Key Responsibilities

- Own the end-to-end IP packaging, release, versioning, and lifecycle-management process.
- Generate, validate, and maintain design views such as schematic, symbol, layout, extracted, CDL/SPICE netlists, and behavioral/AMS models.
- Create and qualify physical views and release collateral, including LEF/abstract, GDS, integration guides, documentation, and release notes.
- Generate and validate timing views, including Liberty (.lib), multi-PVT libraries, and relevant timing characterization deliverables.
- Generate and validate power views, including leakage, agile power, multi-PVT power models, and related characterization collateral.
- Develop automated checks for pin, connectivity, hierarchy, interface, naming, version, PVT coverage, and cross-view consistency.
- Build automation frameworks for view generation,



release validation, regression execution, quality reporting, and documentation.
- Define reusable methodologies, quality gates, sign-off criteria, and configuration-management practices across IP programs.
- Collaborate with Design, Layout, Verification, CAD, Characterization, Physical Implementation, and SoC Integration teams.

Qualifications &

Skills

- B.E./B.Tech/M.E./M.Tech in Electronics, Electrical, Computer Engineering, or a related field.
- 10+ years of experience in IP methodology, CAD, design automation, IP packaging, library management, or semiconductor design infrastructure.
- Strong scripting skills in Python, SKILL, TCL, Perl, or Shell.
- Experience with custom-IC EDA environments, IP repositories, version control, regression systems, and release-management flows.
- Familiarity with timing, power, physical, functional, and verification views used for SoC integration.
- Knowledge of Analog/Mixed-Signal design flows is preferred; hands-on analog circuit design is not required.

📌 Senior AMS IP Methodology & Infrastructure Engineer (Bengaluru)
🏢 Lu0026T Semiconductor Technologies
📍 Bengaluru