We are hiring for one of our reputed clients for the following position. If you're interested and your experience matches the requirement, we'd love to hear from you.
Key Responsibilities & Skills:
Solid hands-on SystemVerilog (SV) and UVM expertise.
Experience in UVM-based verification, test development, regression and debugging.
Must have DDR or PHY Verification experience.
Positive-to-have exposure to GLS, Co-Simulation, Formal Verification and SVA/Assertion-Based Verification.
Robust understanding of verification methodologies and debugging complex failures.
Education: B.E./B.Tech/M.E./M.Tech in Electronics & Communication.