Sta Engineer Asic Full Chip Timing Analysis Bengaluru (India)

Sta Engineer Asic Full Chip Timing Analysis Bengaluru (India)

03 Sep
|
Agile Ventures
|
India

03 Sep

Agile Ventures

India

Job Description:

HBM Blocks
Operational-based clock creation.
Experience required in deep timing analysis.
Tools: PrimeTime, virtuse symatic
Develop timing constraints and perform Static Timing Analysis (STA).
Schematic Tracing
Full Chip Timing Analysis
Hands-on experience in full-chip level timing analysis.
ASIC Background
Solid ASIC design/verification background preferred.

Positive to have: Experience with Virtuoso Schematic tracing.

Experience:
Robust profile with 4+ yrs' experience.
Minimum experience: 4 years.

Qualification:
B.E. / M.Tech

📌 Sta Engineer Asic Full Chip Timing Analysis Bengaluru (India)
🏢 Agile Ventures
📍 India

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