Candidate Qualifications

Minimum qualifications
Bachelor’s degree in Electrical Engineering or Computer Science
Verilog/SystemVerilog based verification experience at Subsystem and Full chip level.
Experience with SOC Emulation a plus

Preferred Qualifications
Bachelor’s degree in Electrical Engineering or Computer Science with 4 -7 years of relevant experience, or Master’s degree in Electrical Engineering or Computer Science with 3 – 6 years of relevant experience.
Experience with digital system based on AMBA Bus protocols like ACE/AXI/AHB/APB or similar complexity bus protocols.
Experience with System Verilog Assertions with industry standard tools a plus
Experience with SOC boot flow, clocking and platform bring up in Emulators or Silicon desired
Experience with Low Power Verification and power management flows.
Experience with RTL, GLS level simulations




Emulation experience with industry standard emulators/FPGA based prototyping platforms
Experience in Methodology Development is a definite plus

Roles & Responsibilities
Be part of a team to verify or emulate complex system on a chip designs. Interact with design engineers to identify significant verification scenarios.
Create and enhance constrained-random verification settings using UVM/ SystemVerilog
Create complex C tests using reusable C test libs.
Synthesis, PNR and timing analysis of RTL on industry standard prototyping and emulation platforms
Create testplans, write and debug tests for functional verification and emulation platforms
Team player, willing to learn and adapt to recent technologies and solutions

Location: Bangalore, India

📌 Soc Senior Design Verification/emulation Engineer Bengaluru (India)
🏢 Mettlesemi Systems and Technologies Private
📍 India