You will contribute to developing Cisco's progressive data center solutions by crafting industry-leading sophisticated chips, with full exposure to all aspects of our systems and applications, including silicon, hardware, software, telemetry, and security. Specific responsibilities include:
Architect block, cluster and top-level DV setting infrastructure.
Develop DV infrastructure from scratch.
Maintain and improve existing DV settings.
Develop test plans and tests for qualifying design at block, cluster and higher-level environments with mix of constraint random and advised stimulus.
Ensure complete verification coverage through implementation and review of code and functional coverage.
Ensure RTL quality with qualifying the design with Gate Level Simulations on netlist.
Collaborate closely with designers, architects, and software teams to address and debug issues during post-silicon bring-up, ensuring seamless integration and effective performance.
Support testing of design in emulation.
Lead all aspects of and manage the ASIC bring-up process.
Minimum Qualifications
Bachelor's degree or master's degree in equivalent experience in EE,
CE, or other related field.
10+ years of related ASIC design verification experience.
Proficient in ASIC verification using UVM/System Verilog.
Proficient in verifying sophisticated blocks, clusters and top level for ASIC.
Experience building test benches from scratch, hands on experience with System Verilog constraints, structures and classes.
Scripting experience with Perl and/or Python.
Preferred Qualifications
Experience with Networking ASICs would be an advantage
Experience with Forwarding logic/Parsers/Buffer management/Arbitration and scheduling
Experience with Veloce/Palladium/Zebu/HAPS.
Formal verification (iev/vc formal) knowledge.
Demonstrated ability on one or more protocols (PCIe, Ethernet, RDMA, IPv4/6, TCP).
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