5 to 8 years of experience in RTL Synthesis, Timing Constraints / SDC checking / reviewing / small fixes / finding errors etc. Should have done at least 3 ASIC projects. CDC, Lint clean up and automation with scripts. Timing Report analysis, Static Timing Analysis Tools : Genus / FC : Synthesis, Optimization or DC compiler, DCTopo Spyglass : Constraints checking / CDC Checking LEC / Formality : Formal Verification, VCLP. Primetime : Zero delay Timing analysis.