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FCT LEAD
The Role
As an FCT Lead within the Physical Design organisation, you will lead Full Chip Timing (FCT) execution and timing signoff activities for complex SoC and subsystem designs. You will work closely with Architecture, Design, PD, STA, DFT, CAD and Methodology teams to achieve first-pass silicon success and deliver timing closure for industry-leading products
The Person
A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented,
possessing good communication and problem-solving skills.
Key Responsiblities
Lead the Full Chip Timing team responsible for timing constraints development and timing signoff.
Own end-to-end timing closure and signoff for SoC and subsystem integration projects.
Define, develop and validate SDC constraints, clocks and timing methodologies.
Drive timing convergence across synthesis, P&R;, CTS, route and post-route ECO stages.
Partner with Architecture and STA teams to establish timing budgets, statistical timing targets and signoff criteria. Analyze and manage advanced-node timing margins including LVF, SSTA, OCV/AOCV/POCV and variation-aware signoff methodologies.
Lead timing ECO planning and execution to ensure on-time tapeout.
Collaborate with CAD and EDA vendors to improve timing closure flows, automation and methodologies.
Mentor engineers and provide technical leadership for timing closure activities across multi
📌 FCT PD lead (Bengaluru)
🏢 AMD
📍 Bengaluru