Job Description: In Arm's Solutions Engineering group, our primary focus extends beyond the development of advanced System-on-Chips (SoCs). In the endeavour to deliver a quality silicon we need to ensure all our signoff checks across various domains are diligently performed. Delivering quality silicon leads to quality rewards and every effort and skill is recognized and appreciated at ARM. Our responsibilities also encompass improvising methodologies, influencing EDA tools and build a knowledge base which will help in our product design. Learning and sharing knowledge is part of ARM culture and is very much appreciated and encouraged. If your interested in working with a team of cooperative and smart engineers responsible for validating RTL-to-Gate and Gate-to-GDS implementations, ensuring power intent correctness, and enabling high-quality silicon tapeout
Responsibilities
Low Power structural check
Perform low-power verification using Cadence Conformal Low Power (CLP) or Synopsys VCLP.
Verify and validate UPF implementation across RTL, netlist, and physical design stages.
Perform power-aware equivalence checking and resolve identified issues.
Analyze, debug, and resolve CLP structural, rule-based, and power-aware verification failures.
Implement SoC-level low-power structural checks and debug issues through closure.
Logical Equivalence Checking (LEC/Formality)
Perform RTL-to-Synthesis, Synthesis-to-P&R;, and ECO logic equivalence verification using Cadence Conformal LEC.
Analyze, debug, and resolve non-equivalences and aborts across different stages of the design flow.
Develop, automate, and maintain robust LEC flows and signoff methodologies.
Drive LEC failure resolution and closure, and generate comprehensive signoff reports.
Implement and debug SoC-level flat LEC runs through signoff.
Methodology And Automation
Develop TCL, Perl, and Python scripts to automate verification tasks and improve productivity.
Build and maintain reusable verification flows and
📌 Senior Engineer (Bengaluru)
🏢 ARM
📍 Bengaluru