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Experience: 2+ yrs
Location: chennai,hyderabad,bangalore
Job Type: Full-time
We are looking for a skilled FPGA Design Verification Engineer with hands-on experience in the Xilinx Vivado implementation flow to validate and test FPGA implementation stages, including placement and Static Timing Analysis (STA).
The ideal candidate will have a robust understanding of FPGA design flows, digital and logic design, STA, design constraints, and debugging. You will be responsible for validating implementation flows, identifying issues, analysing results, and collaborating with engineering teams to ensure reliable and efficient FPGA designs.
Key Responsibilities
Validate and test Xilinx Vivado FPGA implementation flows across different stages.
Work with Vivado implementation stages including placement and Static Timing Analysis (STA).
Analyse implementation results and identify potential design, timing, and flow-related issues.




Validate FPGA designs against defined implementation and timing requirements.
Perform Static Timing Analysis and analyse timing reports, paths, violations, and constraints.
Work with design constraints and verify their correctness and impact on implementation.
Debug logic, timing, placement, and implementation-related issues.
Analyse failures and collaborate with design and verification teams to identify root causes.
Develop and execute test scenarios to validate Vivado implementation functionality and robustness.
Support FPGA design-flow validation across different design configurations and use cases.
Collaborate with digital design, FPGA, verification, and EDA teams to resolve technical issues.
Review implementation reports and provide actionable technical feedback.
Contribute to improving implementation-flow validation, testing methodologies, and debug processes.
Explore opportunities for test automation and scripting to improve validation efficiency.
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📌 FPGA Engineer (Chennai)
🏢 Weekday AI
📍 Chennai