Company

Qualcomm India Private Limited

Job Area

Engineering Group, Engineering Group > Hardware Engineering

General Summary

This position is for RTL designer role in DSP processor team. The position involves in-depth understanding of the ASIC design flow from RTL to GDS2 and the challenges posed by advanced technologies. The successful candidate will possess detailed understanding of RTL design, synthesis, static timing analysis, formal verification, PLDRC, clock domain crossing, and low power techniques. Knowledge and experience of microprocessor integration is a definite advantage.

Skills/Experience

Must have 3 to 15 years of practical experience with details of RTL development (VHDL and/or Verilog) including:

functional and structural RTL design, design partitioning,

simulation and regression, collaboration with design verification team. Must have good familiarity with latest RTL languages and tools, including: simulation systems (e.g. Modelsim, VCS), synthesis tools (e.g. Design Compile), static timing tools (e.g. Prime Time), Linting tools, CDC tools, UPF, code coverage,



System Verilog Assertion, etc.

Experience With The Following Area Is Highly Desirable

Robust processor architecture knowledge
Microarchitecture implementation
Microprocessor integration
Low power design

Responsibilities

Develop RTL for multiple logic blocks of a DSP core

Run various frontend tools to check for linting, clock domain crossing, synthesis, etc.

Work with physical design team on design constrain and timing closure

Work with power team on power optimization

Work with verification team to collaborate on test plan, coverage plan, and coverage closure

Minimum Qualifications

Bachelor's degree in Electrical/Electronics Engineering, Computer Engineering, or related field and 3+ years of Hardware Applications Engineering or Hardware Design experience or related work experience.

OR

Master's degree in Electrical/Electronics Engineering, Computer Engineering, or related fi

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