About The Role

DesignNex is looking for highly motivated interns to join our Physical Design (PD) team. This internship provides a hands-on learning experience in semiconductor backend design,

allowing you to work on industry-grade ASIC design flows using leading EDA tools.

Exceptional performers may receive full time offers post-internship.

Key Responsibilities

- Work on the RTL to GDSII flow, covering Floorplanning, Placement, CTS, Routing, STA, and Signoff.
- Learn and apply CMOS fundamentals in layout design, power planning, and timing closure.
- Utilize Linux environments for scripting and automation (Shell, Perl, or Python).
- Work with industry-standard EDA tools for Physical Design and Timing Analysis.
- Collaborate with senior engineers for debugging and optimizing designs.

Most Important Concepts

You’ll Learn &
- Apply
- Setup and Hold Concepts in STA –
- Understanding timing violations, clock skew, and margin optimization.
- Physical Design Methodology –
- Exposure to industry best practices in floorplanning, power planning,



congestion handling, and signoff strategies.
- Physical Design Inputs –
- Working with netlists, constraints, technology files, and design rules for backend implementation.

Required

Skills

- CMOS Fundamentals –

- Strong grasp of MOSFETs, leakage, power, and timing concepts.
- Linux Proficiency –
- Familiarity with command-line operations, scripting, and automation.
- Physical Design Basics –
- Awareness of RTL to GDSII flow and VLSI concepts.
- Scripting Knowledge –
- Tcl, Python, or Perl for design automation (a plus).
- Problem-Solving Skills –
- Strong analytical mindset and eagerness to learn in a fastpaced environment

Why Join Us?

- Work on real semiconductor projects with industry experts.
- Learn from experienced mentors in the VLSI domain.
- Gain hands-on PD exposure and networking opportunities.
- Potential full-time employment based on performance.

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🏢 DesignNex
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