Design Verification Eng 2 (Pune)

Design Verification Eng 2 (Pune)

06 Sep
|
Lattice Semiconductor
|
Pune

06 Sep

Lattice Semiconductor

Pune

Lattice Overview

There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D;, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.

Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.

Responsibilities

Job Description:

Inviting candidates with a passion for invention and self-challenge.



This position gives you an opportunity to be a part of one of the most cutting edge and key projects that Lattice’s Silicon Engineering team has embarked upon to date. As part of our team, you will have the chance to contribute to verifying complex FPGAs. This team will allow you to integrate multiple sophisticated IP level Design and Verification (DV) environments, craft highly reusable best-in-class UVM TB, implement effective coverage driven and directed test cases, deploy new tools and implement methodologies to improve quality of tape-out readiness. By collaborating with other product development teams across Lattice, you can push the industry boundaries of what FPGA systems can do and improve the product experience for our customers across the world You will be able to learn all aspects of a FPGA, different types of SOC architecture, many highspeed layered protocols, industry’s standard methodologies on low power architecture, best in class

📌 Design Verification Eng 2 (Pune)
🏢 Lattice Semiconductor
📍 Pune

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