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Experience: 4+ yrs
Location: Bengaluru
Job Type: Full-time
We are looking for a skilled SoC Design Verification Engineer with strong hands-on expertise in PCIe Gen5 protocol verification to contribute to pre-silicon verification of complex semiconductor designs.
The role involves verifying PCIe functionality across IP, subsystem, SoC, and full-chip levels using SystemVerilog and UVM. The ideal candidate will have robust protocol knowledge, excellent debugging capabilities, and experience driving verification coverage and sign-off for complex SoC designs.
Key Responsibilities
Develop detailed verification plans, test scenarios, and test strategies for PCIe Gen5 functionality.
Build, enhance, and maintain SystemVerilog/UVM-based verification environments.
Verify PCIe protocol functionality across IP, subsystem, SoC, and full-chip levels.
Validate key PCIe features including LTSSM, link training, TLP, DLLP, enumeration, configuration, and error handling.
Perform functional,



protocol compliance, and integration-level verification.
Develop SystemVerilog Assertions (SVA) and functional coverage models.
Execute simulation regressions and analyze failures to drive coverage closure.
Debug complex PCIe protocol, RTL, and integration issues across multiple design levels.
Collaborate closely with RTL designers, architects, firmware engineers, and other verification teams.
Identify verification gaps and contribute to improving test environments, methodologies, and automation.
Track coverage, defects, and verification progress throughout the project lifecycle.
Support SoC/full-chip verification sign-off and ensure verification objectives are achieved before tape-out.
What Makes You a Great Fit
4+ years of experience in semiconductor design verification or a related field.
Mandatory: Strong hands-on experience in PCIe Gen5 protocol verification.
Strong proficiency in SystemVerilo

📌 SoC Design Verification Engineer (Bengaluru)
🏢 Weekday AI
📍 Bengaluru