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AECG ASIC Physical Design & Implementation Engineer :
THE ROLE:
The focus of this role in the AECG ASIC organization is to lead physical design for next generation ASICs that meet Engineering, Business and Customer requirements.
Engineer with good attitude who seeks new challenges and has good analytical and communication skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player.

THE PERSON:
AMD is looking for an engineering leader passionate about driving the best Power Performance Area (PPA)



of ASIC solutions for AECG customers. The ideal candidate will have proven experience in driving physical design optimization to deliver industry leading performance/area and performance/power. In this role the candidate will work with the customer, SOC architects, the CAD team and the design team and drive floorplanning and physical design flows for best in class ASIC solutions.

KEY RESPONSIBLITIES:
Implementing RTL to GDS2 flow
Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR, Formal Equivalence
Deft at Handling different PNR tools - Synopsys Fusion Compiler, ICC2, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk, Cadence Genus, Innovus.
Tasks to include Full Chip Level Floor planning, Bus / Pin Planning, feed-thru planning, Cloc

📌 ASIC Physical Design (Bengaluru)
🏢 Advanced Micro Devices
📍 Bengaluru