Rtl - fpga design engineer (Hyderabad)

Rtl - fpga design engineer (Hyderabad)

06 Sep
|
ACL Digital
|
Hyderabad

06 Sep

ACL Digital

Hyderabad

RTL & FPGA Design Engineer
Experience : 4-6 years
Location : Hyderabad
Core Skills: RTL Digital Design (Verilog/VHDL), Vivado toolchain (Design creation to Bitstream generation), and timing/IO constraints.
Architecture & Interfaces: Strong grasp of AXI/AHB/CHI/ACE5 buses, peripherals (USB, Ethernet), and Video IPs (ISP/Encoder/Decoder).
Debugging & Tools: Industry-standard front-end waveform debugging, ILA, Unix workplace, and scripting (Tcl/Python/Perl).
Bonus: Hands-on experience with pre-silicon platforms and automated verification flows.
Interested candidates, please send your resume to janagaradha.n@

📌 Rtl - fpga design engineer (Hyderabad)
🏢 ACL Digital
📍 Hyderabad

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