Senior Faculty – Design Verification (Hyderabad)

Senior Faculty – Design Verification (Hyderabad)

06 Sep
|
MOSart Labs
|
Hyderabad

06 Sep

MOSart Labs

Hyderabad

Senior Design Verification Faculty

Location: Hyderabad – Work From Office | Monday to Saturday | Full-Time

Reports To: Head – Academics / Training Delivery

About MOSart Labs

MOSart Labs is a leading Semiconductor Training & Chip Design company focused on building industry-ready VLSI engineers through hands-on, industry-focused training. Our programs include Design Verification, Physical Design, RTL Design, IIT Bhubaneswar PG Diploma and Zero to Silicon programs, with industry-tool exposure, projects and mentorship from semiconductor professionals.

Role

We are looking for an experienced Senior Design Verification Faculty with 5–10 years of semiconductor industry experience and a solid passion for teaching and mentoring.

This is a full-time teaching role responsible for delivering offline classroom training, hands-on labs, student mentoring, assessments, project guidance, and placement preparation in Design Verification and Advanced Design Verification.

Key Responsibilities
- Deliver classroom training on Design Verification and Advanced Design Verification.




- Conduct hands-on labs using SystemVerilog, UVM and industry-standard EDA tools.
- Teach concepts through practical examples, live coding, simulation and debugging.
- Guide mini-projects and industry-level verification projects from planning to verification closure.
- Mentor students on technical concepts, projects, internships and placement preparation.
- Develop and update course content, lecture materials, lab manuals, assignments, assessments and project statements.
- Conduct technical evaluations, project reviews and doubt-clearing sessions.
- Track student performance and provide technical guidance.
- Stay updated with latest verification methodologies, protocols, tools and industry practices.
- Collaborate with internal technical teams to continuously improve the curriculum.

Subject Expertise Required

Design Verification
- SystemVerilog Fundamentals
- Testbench Development
- Constrained Random V

📌 Senior Faculty – Design Verification (Hyderabad)
🏢 MOSart Labs
📍 Hyderabad

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