Description
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Experience: 4+ yrs
Location: Hyderabad
Job Type: Full-time

We are looking for an experienced Senior SoC / Full-Chip Design Verification Engineer with robust expertise in Gate-Level Simulation (GLS), SystemVerilog, and UVM. The role will focus on pre-silicon verification of complex SoC and full-chip designs, ensuring functional correctness, design robustness, and readiness for silicon.
The ideal candidate will have hands-on experience in GLS, verification environments, regression, debugging, and digital design concepts, with the ability to work on complex verification challenges across the chip development lifecycle.

Requirements
Key Responsibilities
- Perform Gate-Level Simulation (GLS) for SoC and full-chip designs.
- Develop and maintain verification environments using SystemVerilog and UVM.
- Execute pre-silicon verification for complex digital designs and SoC architectures.
- Develop, enhance, and maintain testbenches, test scenarios,



and verification components.
- Analyze simulation results and debug functional, timing, and design-related issues.
- Run and maintain regression suites to identify failures and verification gaps.
- Collaborate with RTL designers, architects, and verification teams to resolve design issues.
- Verify complex digital circuits and ensure design functionality against specifications.
- Develop verification plans, test strategies, and coverage-driven verification methodologies.
- Analyze simulation logs, waveforms, and failure patterns to identify root causes.
- Contribute to verification automation and improve regression efficiency.
- Support verification sign-off activities and ensure adequate functional and code coverage.
- Apply assertions/SVA and other verification techniques where applicable.
- Support verification of memory controllers, DRAM interfaces, or other complex subsystems when required.
- Contribute to low-

📌 Design Verification Engineer (Hyderabad)
🏢 Weekday AI
📍 Hyderabad