Memory Layout Engineers (Bengaluru)

Memory Layout Engineers (Bengaluru)

06 Sep
|
ACL Digital
|
Bengaluru

06 Sep

ACL Digital

Bengaluru

Job Description
We are hiring experienced Memory Layout Engineers (3–18 yrs) with expertise in ARM architectures and advanced nodes (7nm, 5nm, 2nm). The ideal candidate brings a robust foundation in memory compilers, general memory concepts, and hands-on physical design on lower process technologies. Location: Bangalore & Hyderabad ⏱️ Notice Period: 0–15 Days (Immediate joiners preferred) To Apply: Send your updated CV to [email protected]

📌 Memory Layout Engineers (Bengaluru)
🏢 ACL Digital
📍 Bengaluru

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