06 Sep
|
Anlage Infotech India Private
|
Bengaluru
06 Sep
Anlage Infotech India Private
Bengaluru
We are looking for an experienced Design Verification (DV) Design Lead with strong expertise in PCIe SystemC IP / Subsystem Verification to drive high-quality pre-silicon verification and ensure robust, bug-free silicon.
The ideal candidate will have strong hands-on experience in SystemVerilog, UVM, functional and formal verification , verification planning, coverage closure, regression automation, and verification sign-off. Experience with mixed-signal IP, RNM/Verilog-A, C/MATLAB modelling, Specman e, and functional safety (ISO 26262) will be highly valued.
Key Responsibilities
- Lead and execute pre-silicon verification activities for PCIe SystemC IPs and subsystems.
- Develop and maintain high-quality SystemVerilog/UVM-based verification environments .
- Create detailed verification plans , define verification strategies, and drive execution.
- Develop and execute functional and formal verification methodologies.
- Drive functional coverage, code coverage, and coverage closure activities.
- Develop, debug, and maintain test cases suitable for regression.
- Run verification regressions and support the setup and automation of continuous regression environments .
- Analyze failures, perform root-cause analysis, and provide debug support to achieve verification sign-off.
- Prepare verification progress reports, KPI reports, and verification sign-off documentation.
- Work closely with cross-functional teams including design, architecture, modelling, and validation teams.
- Support verification workplace qualification and ensure compliance with defined quality KPIs.
- Contribute to regression automation using Jenkins and scripting languages .
- Support Certitude closure and other formal/functional verification closure activities.
- Work effectively with international and multicultural technical teams.
Required Skills & Experience
- 7–20 years of experience in semiconductor design verification .
- Strong hands-on experience in SystemVerilog and UVM .
- Proven experie
📌 Design Verification Design Lead – PCIe (Bengaluru)
🏢 Anlage Infotech India Private
📍 Bengaluru