Senior Memory Layout Engineer Location: Experience: 5–10 Years We are looking for experienced Senior Memory Layout Engineers with strong hands-on expertise in custom layout and physical implementation of memory circuits. The role involves working closely with circuit design, technology, and verification teams to deliver high-quality, DRC/LVS-clean memory layouts. Execute block-level and full-memory layout from schematic/netlist to DRC/LVS-clean database . Ensure adherence to foundry PDK, design rules, and layout methodologies . Participate in design reviews, tapeout activities, and continuous layout methodology improvements. 5–10 years of relevant experience in Memory / Custom IC Layout. ~ Strong hands-on experience with SRAM and/or memory macro layout .



~ Valuable understanding of CMOS layout concepts, device matching, parasitics, and design rules . ~ Experience with industry-standard tools such as Cadence Virtuoso, Calibre, or equivalent . ~ Good scripting/automation exposure using SKILL, Python, Tcl, or Shell is an advantage. ~ Experience with high-density memory macros and advanced-node technologies . Exposure to full-custom layout, PEX, EM/IR, and reliability checks . Experience working in a tapeout-driven semiconductor environment .

📌 Background Layout Artists (Hyderabad)
🏢 Leadsoc Technologies
📍 Hyderabad