Job Description
Hi All,
n
n Greetings from Eximietas Design...
n
n Eximietas Hiring Principal SoC DFT Engineers | Hyderabad Location.
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n Experience: Min 10+Years.
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n Locations:- Bengaluru, Hyderabad, Ahmedabad & Visakhapatnam.
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n San Jose (Bay Area), USA
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- Eligibility (USA): U.S. Permanent Residents (Green Card holders).n

n
n Job Description:
nWe are seeking motivated Design for Test (DFT) professionals to join our growing team. Whether
nyou are a hands-on technical lead or an industry veteran with architectural expertise, we offer roles
nthat will challenge and grow your skills in advanced silicon testing.
nYou will be responsible for the end-to-end DFT flow, from RTL to final pattern delivery, across
ncomplex IP, subsystem, and SOC designs.
n
n Core Responsibilities:
n End-to-end ownership of the DFT implementation flow from RTL to final pattern sign-off.
n Scan architecture definition and implementation at RTL and gate level, including EDT and
nOCC.
n Execution of block-level ATPG, DRC analysis, and coverage optimization.




n Handling of pattern simulations, including both timing and non-timing simulations.
n SOC-level integration, including pattern retargeting to subsystem and full-chip levels.
n Integration, simulation, and debugging of MBIST, IJTAG, and Boundary Scan (JTAG).
n Independent debugging of DFT simulations and netlist-related issues.
n Close collaboration with design, verification, and physical design teams to ensure DFT
nreadiness.
n Ownership of DFT sign-off activities and deliverables.
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n Key Responsibilities:
n Develop and implement robust DFT architectures for IP, subsystem, and SOC designs.
n Perform scan insertion, ATPG generation, and pattern validation at block and top levels.
n Analyze and resolve coverage, DRC, and simulation failures to meet quality targets.
n Define and execute DFT strategies aligned with project requirements and schedules.
n Support pre-silicon and post-sil

📌 Principal SoC DFT Engineer_Hyderabad (Hyderabad)
🏢 Eximietas Design
📍 Hyderabad