Skill: DFT - DFT (Design for Test) is a specialized domain in the semiconductor/VLSI industry that ensures integrated circuits (ASICs/SoCs) are testable during manufacturing. DFT engineers design and implement test structures such as Scan, ATPG, MBIST, LBIST, and JTAG to improve chip quality, fault coverage, and manufacturing yield.Key skills to target:End-to-end DFT implementationScan insertion & compression, ATPGMBIST, LBIST, JTAG/Boundary ScanDFT signoff, fault coverage, debuggingRTL, SoC design flow, STATools: Siemens Tessent, Synopsys TestMAX, Cadence ModusScripting: TCL, Python, Perl--------------------------------------------------A DFT Staff Engineer is responsible for designing, implementing, and signing off Design-for-Test (DFT)architecture for complexSoCs/IPs. The roleensures that semiconductor designs are testable, high-quality, and manufacturable, whilebalancing coverage, performance, power, and cost.Key ResponsibilitiesDFT Architecture G StrategyDefine and implement DFT architecture at block/IP or SoC levelSpecify test methodologies (scan,MBIST, boundary scan,compression)Ensure testability built early into RTL design flowBalance trade-offs between coverage, area, power,



and test timeDFT Implementation Perform:Scan insertion and stitchingATPG pattern generation and simulationMBIST / LBIST / boundary scan integrationDevelop and validate DFT timing constraints (STA)Execute DFT flows at RTL and gate levelTest Coverage G ǪualityAnalyze and improve fault coverageDebug scan/ATPG issues and resolve coverageholesOptimize:Pattern countTest costTest timeVerification G SignoffRun DFT verification and DRC checksEnsure clean DFT signoff (coverage, timing, power impact)Validate patterns using simulation and test toolsSupport DFT integration guidelines at SoC levelCross-Functional Collaboration Work with:RTL designPhysical design (PD)VerificationTest engineering / ATEDrive issue resolution acrossteamsEnsure end-to-end execution of DFT flowsSiliconBring-up G DebugSupport post-silicon debug and yield improvementDebug tester failures and improve manufacturing coverageAssist customer or productteams during bring-upRequired Skills G Expertise Core Technical Skills Strong expertise in:Scan (insertion, compression)ATPG C fault modelsMBIST / LBISTJTAG / Boundary Scan (IEEE 1149.1)Valuable understanding of:RTL design C verificationSTA and timing closureSoC designflowToolsSynopsys / Cadence / Siemens tools (e.g., TestMAX, Tessent, Modus)Simulation tools (VCS, etc.)Scripting: TCL, Python, PerlǪualificationsBSEE/MSEE (or equivalent)Typically 7+ years of DFT / ASIC experience (Staff-level expectation)Proven experience in end-to-end DFT implementation and debugging

📌 DFT Engineer in Hyderabad/Bangalore (Vasanth Nagar)
🏢 Makonis
📍 Vasanth Nagar