Job Description
Hiring: Memory Layout Engineers
n Experience: 2–6 Years
n Locations: Bangalore | Noida | Hyderabad
n Notice Period: Immediate Joiners / Short Notice Preferred
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n Key Responsibilities:
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- Hands-on experience in Memory Layout / Custom Layout for SRAM, ROM, NVM or Memory Compiler blocks.n
- Experience in Bitcell, Memory Array, Row/Column Decoder, Sense Amplifier, I/O and Peripheral layouts.n
- Strong knowledge of Floorplanning, Routing, Hierarchical Layout & Layout Optimization .n
- Hands-on experience with DRC, LVS, ERC, Antenna, EM/IR and Physical Verification .n
- Good understanding of CMOS/FinFET technologies, layout rules, matching, parasitics and PPA optimization .n
- Proficiency in Cadence Virtuoso/Virtuoso XL and preferably Calibre .n




- Knowledge of Memory Compiler / Tiling / Automation is an added advantage.n
- Exposure to SKILL / Perl / TCL / Shell scripting is a plus.n

n Education: BE/B.Tech/M.Tech in ECE, EE, VLSI, Microelectronics or related field.
n Ideal Candidate: Memory/Custom Layout Engineer with solid hands-on implementation and physical verification experience. Current industry postings similarly emphasize Virtuoso, DRC/LVS, memory arrays and physical verification.
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n Interested candidates can share their updated CV with:
n Total Experience | Relevant Memory Layout Experience | Current Location | Notice Period | Preferred Location
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📌 Memory Layout Engineer (Bengaluru)
🏢 Leadsoc Technologies
📍 Bengaluru