About the team :

Renesas Electronics Americas (REA) is a agile, multi-cultural tech company where employees can learn, mentor and thrive. REA brings together the strong financial foundation of a multi-billion dollar global operation and the flexibility and velocity of a smaller organization. We are developing technologies for the latest advances in mobile computing, secured connected devices, autonomous driving, smart homes and factories and more. Our solutions are at the heart of products developed by the major innovators around the world. Join us and be part of what s next in electronics.

This is an opportunity to join a top-notch Mobile Power IC (PMIC) Design Team within Renesas Electronics America s leading power management product line. As part of one of Renesas s most prominent Battery and Power Solutions Design Groups, this Engineer will work on next-generation IC products for multiple fast paced consumer power products.

What we need:

The Design team is seeking a Sr. Staff DFT Design Engineer who is technically savvy and is excited about working on cutting edge power solutions for Mobile Application Processors. You will support all design flow tasks and be the champion in managing our processes and systems, interfacing with multiple departments and external customers. Given the wide range of responsibility, we re looking for someone eager to learn, ready to hit the ground running, and help define what Design means for Renesas. This opportunity will allow you to open pathways to by having a greater level of responsibility in the team and across Renesas. If you like problem-solving, building something from the ground up,



and challenging the status quo, we d like to hear from you.

:

- Define and document the comprehensive DFT architecture for multi-core SoCs, including strategies for hierarchical scan compression, Memory BIST (MBIST) for huge memory instances, Functional BISTs, Analog components, Logic BIST, high-speed I/O loopback, and JTAG/IEEE 1149. 1/1500/1687/1838 networks.
- Implementation Verification: Lead the integration of digital subsystems, perform scan insertion, and generate ATPG (Automatic Test Pattern Generation) patterns while ensuring high fault coverage.
- A proven track record in the fields below
- Digital DFT of large and small designs: Scan, MBIST, DFT insertion and ATPG
- Experience with leading DFT/ATPG tools (Synopsys, Mentor)

- Experience and a good understanding in these fields is desirable

- Functional Safety incl. Logic BIST
- ATE and test engineering of mixed-signal ICs
- Non-volatile memory (Flash, MRAM, ReRAM)
- Mixed-signal design (power management, audio, RF)

- Exposure to production test related engineering challenges (yield improvement)
- Command of verbal and written English, ability to use it in a convincing manner for communicating technical concepts
- Ability to assert self while maintaining a cooperative environment within the design team.




- Proven ability to lead cross-functional teams and deliver results in a fast-paced, high-complexity environment
- Hands-on experience with industry-standard EDA tools (e. g. , Synopsys TestMAX, Mentor Tessent)
- Strong understanding of SoC/MCU architecture and digital design flows
- DFT insertion (and generation of test patterns (ATPG)
- Verification of test modes and test patterns prior tapeout
- Validation and debug of test modes and test patterns in the lab or on ATE
- Diagnose fail devices, support PFA.
- Work with Product, Test, and Applications Engineering to complete product release

Qualifications

Skills You ll Need

- B. A. /B. S. in engineering, engineering management, or engineering operations required
- BSc/BEng in Electrical or Electronic engineering, MS or PhD preferred
- Minimum of 8 years industry experience with BS working in DFT digital or mixed signal IC design
- Experience in DFT protocols including Scan Compression, MBIST, LBIST, JTAG (IEEE 1149. 1), and iJTAG (IEEE 1687).
- DFT insertion
- Test coverage, test application time
- Debug effort required by test engineer to reach milestone of patterns running
- First time right success rate

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, or national origin.

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

📌 Senior Staff DFT Engineer (Bengaluru)
🏢 Renesas
📍 Bengaluru