06 Sep
|
BITSILICA
|
India
- 8 to 10+ yrs of experience in DFT architecture, scan Insertion, compression at core level and SoC level.
- Experience in ATPG pattern generation, coverage analysis
- Experience with timing and no-timing simulations
- Experience in Memory-BIST
- Have understanding of SSN architecture, clock architecture, OCC
📌 DFT Lead Engineer (India)
🏢 BITSILICA
📍 India