Role Summary

We are seeking an experienced Senior Analog Design Engineer to design and develop high-performance analog and mixed-signal circuits for next-generation DDR and SerDes PHY IPs targeting advanced FinFET technology nodes. The ideal candidate will have strong expertise in analog circuit architecture, transistor-level design, simulation, and silicon bring-up, with experience in process technologies such as TSMC 16nm and below.

You will work closely with layout, verification, reliability, and system teams to deliver robust, high-speed, low-power analog IPs optimized for performance, manufacturability, and yield.

Key Responsibilities

- Design and develop high-performance analog and mixed-signal circuits for DDR and SerDes PHY IPs.
- Architect and implement transmitter and receiver circuits, including:
- Feed Forward Equalizer (FFE)
- Continuous-Time Linear Equalizer (CTLE)
- Decision Feedback Equalizer (DFE)
- Design precision analog building blocks such as:
- Operational Amplifiers (Op-Amps)
- Bandgap References
- Voltage Regulators (LDOs)
- Charge Pumps
- ADCs
- PLLs
- DLLs
- Clock and Data Recovery (CDR) circuits
- Perform transistor-level schematic design and optimization for power, performance, and area (PPA).
- Conduct comprehensive simulations across all PVT corners, Monte Carlo, mismatch, and worst-case operating conditions.
- Collaborate closely with layout engineers to ensure layout-aware design and post-layout optimization.
- Work with verification, reliability, and validation teams to ensure first-pass silicon success.




- Implement ESD-aware circuit design and protection methodologies.
- Drive design-for-manufacturability (DFM), reliability, and yield improvement initiatives.
- Prepare design documentation and support IP integration, characterization, and silicon debug activities.

- Required Qualifications

- Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, VLSI, or a related discipline.
- 5–12 years of experience in analog/mixed-signal IC design.
- Strong experience in designing analog circuits for DDR PHY, LPDDR PHY, GDDR PHY, HBM PHY, or SerDes PHY.
- Hands-on expertise in advanced process nodes, preferably TSMC 16nm, 12nm, 7nm, 5nm, or below.
- Robust understanding of:
- Analog circuit design fundamentals
- High-speed interfaces
- Signal integrity
- Device physics
- Process variation analysis
- Experience performing:
- Pre-layout and post-layout simulations
- PVT corner analysis
- Monte Carlo simulations
- EMIR and reliability analysis
- Good understanding of ESD protection techniques and reliability considerations.

Required Tools

- Cadence Virtuoso / Artist
- Cadence ADE
- Spectre Simulator
- EMIR and Reliability Analysis Flows
- LVS/DRC debugging and post-layout verification tools

Preferred Skills

- Experience with DDR4, DDR5, LPDDR4, LPDDR5, HBM, PCIe, Ethernet, or other high-speed interface PHYs.
- Knowledge of FinFET design methodologies and advanced CMOS technologies.
- Exposure to silicon bring-up, characterization, and lab validation.
- Strong debugging and analytical skills.
- Excellent communication and cross-functional collaboration abilities.

📌 Circuit Design Engineer (Bengaluru)
🏢 leadIC Design
📍 Bengaluru