Job Description
Exp level: 2 to 5 years
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Location: Bangalore
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Notice Period: Immediate joiners are preffered.
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Responsibilites:
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- Design and implement analog layouts for high-performance circuits (e.g., amplifiers, ADCs, DACs, voltage regulators) using TSMC 3nm and 5nm nodes.
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- Perform design rule checks (DRC), layout versus schematic (LVS), and electrical rule checks (ERC) to ensure design compliance.
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Required Skills:
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- Solid experience in analog layout design at advanced nodes (TSMC 3nm and 5nm).
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- Proficiency in layout tools like Cadence Virtuoso, Synopsys IC Compiler, or similar.
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- Understanding of layout-dependent effects (LDE) and its impact on performance.
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- Knowledge of parasitic extraction, simulation, and optimization.
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- Familiarity with design for manufacturability (DFM) techniques.
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Please email Resumes to
[email protected]
📌 Analog layout Engineer (Bengaluru)
🏢 ACL Digital
📍 Bengaluru