Job Description

Skill: DFT - DFT (Design for Test) is a specialized domain in the semiconductor/VLSI industry that ensures integrated circuits (ASICs/SoCs) are testable during manufacturing. DFT engineers design and implement test structures such as Scan, ATPG, MBIST, LBIST, and JTAG to improve chip quality, fault coverage, and manufacturing yield.

n

n

Key skills to target:

n

n
- End-to-end DFT implementation
n
- Scan insertion & compression, ATPG
n
- MBIST, LBIST, JTAG/Boundary Scan
n
- DFT signoff, fault coverage, debugging
n
- RTL, SoC design flow, STA
n
- Tools: Siemens Tessent, Synopsys TestMAX, Cadence Modus
n
- Scripting: TCL, Python, Perl
n

n

n

--------------------------------------------------

n

A DFT Staff Engineer is responsible for designing, implementing, and signing off Design-for-Test (DFT)architecture for complexSoCs/IPs. The roleensures that semiconductor designs are testable, high-quality, and manufacturable, whilebalancing coverage, performance, power, and cost.

n

Key Responsibilities

n

n
1. DFT Architecture G Strategy
n

nn
- Define and implement DFT architecture at block/IP or SoC level
n
- Specify test methodologies (scan,MBIST, boundary scan,compression)
n
- Ensure testability built early into RTL design flow
n
- Balance trade-offs between coverage, area, power, and test time
n

nn
1. DFT Implementation Perform:
n

nn
- Scan insertion and stitching
n
- ATPG pattern generation and simulation
n
- MBIST / LBIST / boundary scan integration
n
- Develop and validate DFT timing constraints (STA)
n
- Execute DFT flows at RTL and gate level
n

nn
1.



Test Coverage G Ǫuality
n

nn
- Analyze and improve fault coverage
n
- Debug scan/ATPG issues and resolve coverageholes
n
- Optimize:
n
- Pattern count
n
- Test cost
n
- Test time
n

nn
1. Verification G Signoff
n

nn
- Run DFT verification and DRC checks
n
- Ensure clean DFT signoff (coverage, timing, power impact)
n
- Validate patterns using simulation and test tools
n
- Support DFT integration guidelines at SoC level
n

nn
1. Cross-Functional Collaboration Work with:
n

nn
- RTL design
n
- Physical design (PD)
n
- Verification
n

n

n

n
- Test engineering / ATE
n
- Drive issue resolution acrossteams
n
- Ensure end-to-end execution of DFT flows
n

nn
1. SiliconBring-up G Debug
n

nn
- Support post-silicon debug and yield improvement
n
- Debug tester failures and improve manufacturing coverage
n
- Assist customer or productteams during bring-up
n

n

Required Skills G Expertise Core Technical Skills Strong expertise in:

n

n
- Scan (insertion, compression)
n
- ATPG C fault models
n
- MBIST / LBIST
n
- JTAG / Boundary Scan (IEEE 1149.1)
n
- Positive understanding of:
n
- RTL design C verification
n
- STA and timing closure
n
- SoC designflow
n

n

Tools

n

n
- Synopsys / Cadence / Siemens tools (e.g., TestMAX, Tessent, Modus)
n
- Simulation tools (VCS, etc.)
n
- Scripting: TCL, Python, Perl
n

n

Ǫualifications

n

n
- BSEE/MSEE (or equivalent)
n
- Typically 7+ years of DFT / ASIC experience (Staff-level expectation)
n
- Proven experience in end-to-end DFT implementation and debugging
n

n

📌 DFT Engineer in Hyderabad/Bangalore (Bengaluru)
🏢 Makonis
📍 Bengaluru