Job Role: STA Engineer
Exp: 4+ Years
Notice Period: Immediate to 15 days
Location: Bangalore
Key Skills:
✅ 4+ years of STA and timing closure experience on ASIC/SoC designs
✅ Robust expertise in Setup/Hold analysis, MMMC, OCV/AOCV/POCV, CRPR, SI, and timing signoff
✅ Hands-on experience with SDC constraints, timing exception validation, and ECO closure
✅ Proficiency in PrimeTime/Tempus and Tcl scripting
✅ Experience in subsystem/block-level timing signoff and advanced technology nodes
✅ Good understanding of CTS, extraction, IR-drop, crosstalk, low-power (UPF), and physical design impacts on timing
⭐ Prior Intel project experience is preferred