08 Sep
|
BITSILICA
|
Bengaluru
08 Sep
BITSILICA
Bengaluru
8 to 10+ yrs of experience in DFT architecture, scan Insertion, compression at core level and So C level. Experience in ATPG pattern generation, coverage analysis Experience with timing and no-timing simulations Experience in Memory-BISTHave understanding of SSN architecture, clock architecture, OCC
📌 Dft Lead Engineer (Bengaluru)
🏢 BITSILICA
📍 Bengaluru