Primary purpose of the role The role involves taking existing FPGA design documentation, signal-mapping sheets and Proto-1 hardware from partially drafted specifications through to a working, timing-clean and system-validated FPGA implementation. The position will develop high-speed data-processing pipelines, interface with ADCs, DACs and communication peripherals, implement robust clock-domain and reset architectures, and collaborate closely with Hardware, Embedded Software and Application teams. This is a hands-on individual contributor role requiring robust expertise in VHDL, AMD Xilinx FPGA architecture, Vivado, high-speed data acquisition, timing closure, CDC, LVDS interfaces and hardware debugging. Major responsibilities:1. RTL Design & FPGA Implementation2. Clocking, CDC & Reset Architecture3. High-Speed LVDS & Data Capture4. Timing Closure & FPGA Optimisation5. Verification & Validation6. Hardware Bring-Up & Debugging7. FPGA Configuration & Release Management8. Cross-Functional Collaboration9. Documentation & Design Governance

📌 Field-programmable Gate Arrays Engineer (Mumbai)
🏢 Metal Power Analytical
📍 Mumbai