Job Description
Primary purpose of the role
nThe role involves taking existing FPGA design documentation, signal-mapping sheets and Proto-1 hardware from partially drafted specifications through to a working, timing-clean and system-validated FPGA implementation . The position will develop high-speed data-processing pipelines, interface with ADCs, DACs and communication peripherals, implement robust clock-domain and reset architectures, and collaborate closely with Hardware, Embedded Software and Application teams.
nThis is a hands-on individual contributor role requiring robust expertise in VHDL, AMD Xilinx FPGA architecture, Vivado, high-speed data acquisition, timing closure, CDC, LVDS interfaces and hardware debugging.
n
n Major responsibilities:
n1. RTL Design & FPGA Implementation
n2. Clocking, CDC & Reset Architecture
n3. High-Speed LVDS & Data Capture
n4. Timing Closure & FPGA Optimisation
n5. Verification & Validation
n6. Hardware Bring-Up & Debugging
n7. FPGA Configuration & Release Management
n8. Cross-Functional Collaboration
n9. Documentation & Design Governance

📌 Field-Programmable Gate Arrays Engineer (Mumbai)
🏢 Metal Power Analytical
📍 Mumbai