(Staff/Senior Staff Engineer) Backend Integration Engineer /n /n

- Working experience on 7nm and below Technologies.

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- Proficient in Physical Synthesis flow and PPA optimizations with emphasis on Timing and Low Power design.

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- Proficient in Equivalence Checks, Low power Checks.

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- Hands on experience in timing/SDC constraints generation and management and timing report analysis.

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- Co-work with RTL, DFT and PD engineers to meet PPA targets.

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- Hands on experience with Industry Standard tools Fusion Compiler, Genus, Conformal LEC, Formality, Innovus, Primetime etc.

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- Hands on experience with functional ECO flow and implementation.

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- Good understanding of UPF.

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- Familiar with DFT Architecture.

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- Driving current tool evaluation, methodology refinement for PPA optimization for complex subsystem.

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- Proficient in scripting languages TCL/Perl/Python script.

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- Able to work in a diverse team environment and with remote teams.

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- Should be sincere, dedicated, and willing to take up new challenges.

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- Self-starter and highly motivated.

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- Strong debugging, initiative and analysis/problem solving and presentations skills.

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- Interaction with all stake holders which includes weekly/daily status reporting, issue capture and resolution.

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- 6-12 years with MTech or BTech with Top/Block level synthesis, Timing closure (STA), Physical Design or related work experience.

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📌 Synthesis and backend integration engineer (Bengaluru)
🏢 MediaTek
📍 Bengaluru