07 Sep
|
Siliciom Technologies
|
Bengaluru
07 Sep
Siliciom Technologies
Bengaluru
ASIC
Location: Bangalore
Experience: 1 - 5 Years
Required Skills & Knowledge:
B.E/M.E/M.Tech or B.S/M.S in EE/CE.
Responsibilities include RTL development, resolving system level challenges.
Architecting, implementing, documenting and validating the memory controller IP cores.
Experience in verification of complex RTL designs and validating them on the boards is an added advantage.
Working knowledge of UNIX setting and scripting languages (PERL, Python/TCL etc) desired.
Knowledge of AXI/AHB AMBA bus based complex multi-master & slave systems.
Positive waveform debug skills using front end industry standard design tools like VCS, NCSIM and Questa.
Expertise with FPGA architecture and Xilinx implementation tools (Vivado) highly desired.
Excellent communication and problem solving skills.
📌 Rtl Design Engineer: Bengaluru
🏢 Siliciom Technologies
📍 Bengaluru