Physical Verification Engineer (Bengaluru)

Physical Verification Engineer (Bengaluru)

08 Sep
|
Velaura
|
Bengaluru

08 Sep

Velaura

Bengaluru

ROLE OVERVIEW

As a Staff/Sr. Staff Physical Verification Engineer at Velaura AI, you will own
block-level and full-chip physical verification and signoff for next-generation
AI and high-performance computing silicon. You will drive physical verification
from block-level implementation through full-chip integration and final
tape-out, working on complex SoC designs targeting advanced process
technologies.

This is a highly hands-on technical role requiring deep expertise in DRC, LVS,
ERC, PERC, antenna, ESD/EOS, and reliability verification, along with the
ability to identify root causes and implement physical fixes directly in Cadence
Innovus and/or Synopsys Fusion Compiler.

You will work closely with Physical Design, Analog/Mixed-Signal, STA, Power
Integrity, Reliability, I/O, and CAD teams to drive signoff convergence,
establish robust PV methodologies, and achieve first-time-right silicon.

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RESPONSIBILITIES

● Own block-level and full-chip physical verification signoff, including DRC,
LVS, ERC, PERC, antenna, ESD/EOS, and related reliability checks for complex




ASIC/SoC designs.

● Drive tape-out readiness and signoff closure through violation triage,
root-cause analysis, waiver management, schedule tracking, and convergence to
zero or signoff-acceptable violations.

● Execute and debug physical verification using industry-standard tools such as
Siemens Calibre and Synopsys IC Validator (ICV), including complex connectivity,
device-recognition, hierarchy, and advanced-node rule issues.

● Correlate Calibre/ICV results with Cadence Innovus and/or Synopsys Fusion
Compiler implementation databases and drive physical fixes through iterative
verification to closure.

● Perform hands-on physical implementation and ECO changes, including routing
and via edits, metal-shape modifications, cell movement, filler/decap/endcap
updates, power-grid modifications, and other layout changes required for
signoff.

● Define, customize, and enhance PERC and reliability verificat

📌 Physical Verification Engineer (Bengaluru)
🏢 Velaura
📍 Bengaluru

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