Job Description
Job Summary
nWe are looking for a skilled Physical Design Engineer to support end-to-end ASIC/SoC implementation from netlist/RTL to GDSII. The engineer will be responsible for physical implementation, timing closure, PPA optimization, physical verification, and sign-off while working closely with RTL, synthesis, STA, DFT, and verification teams.
nKey Responsibilities
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Execute the complete physical design flow:n
Floorplanningn
Power planningn
Placementn
Clock Tree Synthesis (CTS)n
Routingn
Optimizationn
ECO implementationn
Physical sign-offn
Perform Static Timing Analysis (STA) and resolve setup, hold, transition, and clock violations.n
Analyze and optimize timing, power, area, congestion, and signal integrity.n
Work on MMMC (Multi-Mode Multi-Corner) implementation and timing closure.n
Develop and review timing constraints, including SDC, clocks, generated clocks, and timing exceptions.n
Perform physical verification and sign-off activities including DRC, LVS, antenna, EM/IR, and power integrity checks.n




Debug placement, routing, congestion, timing, and physical-design violations.n
Collaborate with RTL, synthesis, STA, DFT, power, and verification teams to achieve project milestones.n
Support tape-out activities and ensure design quality meets performance, power, area, and reliability targets.n
Develop and improve implementation flows using Tcl/Python/Perl/Shell scripting.n
Participate in methodology development and automation initiatives.n

nRequired Technical Skills
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Solid understanding of ASIC/VLSI Physical Design flow from RTL/Netlist to GDSII.n
Valuable knowledge of:n
Floorplanningn
Placementn
CTSn
Routingn
Timing closuren
ECOn
Physical verificationn
Power planningn
Robust understanding of setup/hold timing and STA.n
Knowledge of MMMC analysis and timing constraints.n
Experience with industry-standard EDA tools such as:n
Cadence Innovu

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