Experience: 7+ Years

Employment Type: Full-Time

Location: Bengaluru

Notice Period: 30 days

About the Role

We are looking for a strong RTL Design Lead who can take ownership of the RTL design and implementation journey through tapeout and GDSII handoff.

In this hands-on leadership role, you will act as the technical bridge between the system/architecture team and external design partners, owning the implementation of the architecture from RTL development through synthesis, timing closure, and final handoff.

You will also build and lead a team of 5–7 RTL engineers, while remaining deeply involved in RTL coding, reviews, synthesis, constraints, and design closure.

Key Responsibilities

- Translate architecture specifications into clean, synthesizable SystemVerilog RTL.
- Own RTL implementation methodology, coding standards, linting rules, and design practices.
- Build and lead a team of 5–7 RTL engineers through the complete design cycle.
- Remain hands-on with RTL development, code reviews, debugging, and optimization.
- Own the synthesis flow using tools such as Synopsys Design Compiler or Cadence Genus.
- Drive timing analysis and closure using PrimeTime or Tempus.
- Define, develop, and maintain SDC timing constraints.
- Review RTL submissions for functionality, synthesizability, coding quality, timing risks, and design robustness.
- Identify and resolve RTL issues including timing hazards, FSM problems, unintended logic, and non-synthesizable constructs.
- Work closely with the verification team to debug functional issues and drive coverage and verification closure.
- Coordinate with external/outsourced design partners for GDSII handoff,



including netlist, constraints, floorplan guidance, and other implementation requirements.
- Work closely with architecture, verification, physical design, DSP, embedded software, and systems teams to ensure successful silicon execution.
- Drive design decisions and resolve technical issues under tight schedule and resource constraints.
- Support the project through RTL freeze, synthesis, timing closure, and final GDSII handoff.

Required Qualifications

- 7+ years of hands-on RTL design experience using SystemVerilog.
- At least one complete tapeout experience through GDSII, with exposure beyond RTL development.
- Solid hands-on experience with synthesis and timing closure.

Experience with

- Design Compiler / Genus
- PrimeTime / Tempus
- SDC constraints
- RTL linting and coding methodology
- Strong experience in processor, DSP, datapath-heavy, or compute-intensive designs.
- Familiarity with advanced semiconductor process nodes, preferably 28nm and below.
- Proven experience reviewing RTL for:
- Timing hazards
- FSM design issues
- Synthesizability
- Coding quality
- Unintended hardware
- Experience leading a small RTL team while remaining technically hands-on.

Good to Have

- Experience with VLIW, vector processors, DSP architectures, or accelerator designs.
- Experience with deterministic or real-time architectures, particularly architectures involving fixed latency or no-cache designs.
- Exposure to formal verification, including SVA and formal verification tools.
- FPGA prototyping experience using Xilinx Vivado.
- Experience working with external design/implementation partners through tapeout.

📌 Senior RTL Design Engineer (Bengaluru)
🏢 leadIC Design
📍 Bengaluru