Senior Memory Layout Engineer /n Location: Hyderabad, India /n Experience: 5–10 Years /n Role Overview: /n We are looking for experienced Senior Memory Layout Engineers with strong hands-on expertise in custom layout and physical implementation of memory circuits. The role involves working closely with circuit design, technology, and verification teams to deliver high-quality, DRC/LVS-clean memory layouts. /n Key Responsibilities: /n /n

- Develop custom layouts for memory circuits including SRAM, ROM, Register File, and memory periphery.

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- Execute block-level and full-memory layout from schematic/netlist to DRC/LVS-clean database .

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- Work on layout of bitcells, sense amplifiers, pre-charge circuits, decoders, write/read paths, and peripheral circuits .

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- Perform matching, symmetry, shielding, common-centroid, and parasitic-aware layout as applicable.

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- Debug and resolve DRC, LVS, ERC, antenna, density, and connectivity issues.

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- Collaborate with circuit designers on layout optimization, PPA, matching, and parasitic reduction .

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- Support PEX and post-layout simulation activities.

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- Ensure adherence to foundry PDK, design rules, and layout methodologies .

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- Participate in design reviews, tapeout activities, and continuous layout methodology improvements.

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- 5–10 years of relevant experience in Memory / Custom IC Layout.

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- Solid hands-on experience with SRAM and/or memory macro layout .

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- Good understanding of CMOS layout concepts, device matching, parasitics, and design rules .

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- Experience with industry-standard tools such as Cadence Virtuoso, Calibre, or equivalent .

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- Strong expertise in DRC/LVS debugging and physical verification .

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- Understanding of FinFET/advanced-node layout concepts is preferred.

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- Good scripting/automation exposure using SKILL, Python, Tcl, or Shell is an advantage.

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- Strong analytical, debugging, and cross-functional collaboration skills.

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- Experience with high-density memory macros and advanced-node technologies .

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- Exposure to full-custom layout, PEX, EM/IR, and reliability checks .

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- Experience working in a tapeout-driven semiconductor environment .

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📌 Senior Memory Layout Engineer (Hyderabad)
🏢 Leadsoc Technologies
📍 Hyderabad