? We’re Hiring | Senior Physical Design Engineer | 5+ Years

We are looking for experienced Senior Physical Design Engineers with solid hands-on expertise in RTL-to-GDSII implementation, timing closure, PPA optimization, and physical signoff to join our VLSI team in #Bengaluru.

? Experience
5+ Years in Physical Design / Physical Implementation

? Key Responsibilities
• Own the complete Netlist-to-GDSII / RTL-to-GDSII physical design flow.
• Handle Floorplanning, Power Planning, Placement, CTS, Routing, and Signoff.
• Drive timing closure across multiple modes and corners.
• Analyze and resolve Setup/Hold, congestion, DRC, LVS, and antenna violations.
• Perform PPA optimization for performance, power, and area.
• Work on CTS optimization, clock skew, latency, and clock balancing.
• Perform Physical ECOs and Timing ECOs.
• Analyze IR Drop, EM, Crosstalk, and Signal Integrity issues.
• Collaborate with STA, RTL, Synthesis, DFT, PV, and methodology teams.




• Support block-level/full-chip implementation, signoff, and tape-out.
• Mentor junior engineers and contribute to methodology improvements.

? Most Important Technical Skills
Physical Design | RTL-to-GDSII | Floorplanning | Macro Placement | Power Planning | Placement | CTS | Routing | MMMC | STA | Timing Closure | Setup/Hold | PPA Optimization | Congestion | SI | Crosstalk | EM/IR | DRC | LVS | Antenna | ECO | Signoff

? Tools
Cadence Innovus | Synopsys ICC2 | Fusion Compiler | PrimeTime | Tempus | Calibre | RedHawk | Voltus

? Scripting
TCL | Perl | Python | Shell Scripting

? Education
B.E./B.Tech/M.E./M.Tech in Electronics & Communication Engineering, Electrical & Electronics Engineering, VLSI, Microelectronics, or a related field.

? Location: Bengaluru
? Experience: 5+ Years
? Domain: VLSI / Semiconductor

📌 Senior Physical Design Engineer (Bengaluru)
🏢 Leadsoc Technologies
📍 Bengaluru