07 Sep
|
SmartSoC Solutions
|
Bangalore Urban
07 Sep
SmartSoC Solutions
Bangalore Urban
Minimum 4+ years of experience with a Bachelor's degree in Engineering studies or Master's degree, robust layout knowledge.
Proficiency in using Cadence tools (Virtuoso Layout, Layout XL, Cadence Schematic Capture, and verification tools - Calibre & Hercules).
Solid layout knowledge in advanced submicron FinFET processes, including TSMC 5nm, 3nm, 2nm, A14 or Samsung lower FinFET nodes.
📌 Senior Memory Layout Engineer Bangalore Urban
🏢 SmartSoC Solutions
📍 Bangalore Urban